Charged-particle beams such as electron beams or ion beams have recently been considered for use in lithography exposure processes for producing sub-micron level semiconductor integrated circuits. FIG. 4 is a schematic diagram depicting a structural configuration and processing sequence of a conventional charged-particle-beam (CPB) exposure apparatus. The CPB exposure apparatus of FIG. 4 includes an exposure-processing chamber 1, a load-lock chamber 3, and an atmospheric chamber 8. The exposure-processing chamber 1 is connected to the load-lock chamber 3 by a first gate valve 2, and the load-lock chamber 3 is connected to the atmospheric chamber 8 by a second gate valve 5. Multiple wafers 6 are stored in a wafer holder 7.
As used herein, the term "wafer" encompasses any sensitive substrate suitable for use in CPB exposure apparatus, such as silicon wafers for semiconductor manufacture, glass plates for liquid crystal displays, and analogous structures.
CPB exposure processing requires that the exposure-processing chamber 1 be maintained under a constant vacuum condition (e.g, 10.sup.-6 Torr). It is therefore necessary to bring each wafer 6 from an atmospheric condition to such a vacuum condition prior to exposure processing in the exposure-processing chamber 1. This is accomplished by the following transport operations. The first gate valve 2 is closed and the second gate valve 5 is opened to bring the load-lock chamber 3 to atmospheric pressure. One of several wafers 6, located at position D in the atmospheric chamber 8, is transported to position C and then to position B in the load-lock chamber 3. The second gate valve 5 is then closed and the load-lock chamber 3 is rapidly evacuated until the pressure inside of the load-lock chamber 3 matches the vacuum condition in the exposure-processing chamber 1. The first gate valve 2 is then opened and the wafer 6 is transported from position B to position A in the exposure-processing chamber 1. The first gate valve 2 is closed, and exposure processing begins in the exposure-processing chamber 1. Meanwhile, the load-lock chamber 3 is returned to atmospheric pressure and another wafer 6 is transported sequentially through positions D-C-B, whereupon the load-lock chamber 3 is evacuated again.
When exposure processing of a wafer 6 is completed, the first gate valve 2 is opened and the processed wafer 6 is removed from the exposure-processing chamber 1 to position E in the load-lock chamber 3, while the unprocessed wafer 6 at position B is transported to position A. The wafer 6 at position E is then transported to position D via position F after the load-lock chamber 3 is returned to atmospheric pressure.
The above transport and exposure processing operations are repeated on multiple respective wafers 6.
When the load-lock chamber 3 is rapidly evacuated the temperature of the gas remaining in the load-lock chamber decreases due to adiabatic expansion. This reduced-temperature gas typically cools the wafer 6 by approximately 2-3.degree. C., causing the wafer 6 to contract. In the case of an 8-inch silicon wafer, the overall diameter of the wafer typically decreases by approximately 0.5 .mu.m per .degree.C. of temperature decrease. If exposure patterns are made on an 8-inch silicon wafer while the temperature of the wafer is different than the operating temperature of the exposure-processing chamber 1, the position of the exposure patterns made in peripheral regions of the wafer will be in error by approximately 0.25 .mu.m per .degree.C. of temperature difference (when compared with an exposure pattern made on an 8-inch silicon wafer that is at the operating temperature throughout exposure). This level of positional error is several orders of magnitude too high for high-level integration semiconductor manufacturing. In order to stay within the desired positional-error limit of 10 nm or less, the wafer temperature must be maintained within .+-.0.02.degree. C. of the operating temperature of the exposure-processing chamber 1.
When the wafer 6 is first transported into the exposure-processing chamber 1, the wafer temperature is less than the operating temperature of the exposure-processing chamber 1, causing the wafer temperature to slowly increase. Exposure processing of the wafer 6 should not be initiated until the temperature of the entire surface of the wafer 6 has stabilized. In the foregoing example of an 8-inch silicon wafer, temperature stabilization may require ten or more minutes per wafer. Such waiting times of this magnitude are intolerable--modern semiconductor manufacturing processes are expected to provide throughput levels of 30-60 wafers/hour, i.e., one wafer every 1-2 minutes. Therefore, the waiting time per wafer must be minimized to achieve such an expected throughput.